module PC(
  input clk,
  input rst,
  input [63:0] next_pc_i,
  input next_pc_valid_i,

  output [63:0] pc_o/*verilator public_flat*/
);

  Reg #(.WIDTH(64), .RESET_VAL(64'h8000_0000)) reg_pc (.clk(clk), .rst(rst), .din(next_pc_i), .dout(pc_o), .wen(next_pc_valid_i));

endmodule
